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· VLSI design engineer that will join Digital Solution group · Taking part in the architecture and implementation of complex: Wireless Networking IPs, physical layer (PHY) transceiver channels, modem blocks, I.P. integration · Working closely with design team developing together the next generation ASIC/FPGA · Working closely with the verification team.


The ideal candidate has the following: Must: · BSc in Computer science/ Electrical engineering · AT least 3-5 years of experience as VLSI Design Engineer with Verilog · Background in Networking IPs and SOC architecture (Ethernet, networking processor, CPU etc) Advantage: · Strong background in signal processing and/or communications protocols-Advantage. (Eth/Pcie/USB etc) · Experience with RISC/DSP/CPU processors. · Experience with synthesis and STA and SDC (Static Timing Analysis. · Experienced in implementation of complex communication IP. (CPU/DSP/Mctrl) · understanding of fix point implementation, modulation, coding, detection, equalization, timing/phase recovery. Tools/Languages: Verilog VHDL, Code Linter, CDC (Cross Domain Clocking), SDC (Synthesis Design Constraint), Altera/Xilinx, Synthesis, STA (Static Timing Analysis), Specman Verification.

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